Analyze process variation and compare it to specifications using graphical tools, control charts, and capability analyses for a semiconductor manufacturing process.
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A semiconductor manufacturer is working on getting seven new etching lines up-and-running at a new facility to satisfy increased demand for chips. A critical step in producing integrated circuits is to etch select areas of an oxide layer from silicon wafers. One important quality metric is Etch Rate. This is the amount of oxide etched from areas of the wafer per unit time, measured in angstroms per minute.
Ideally, all wafers would be etched consistently to target and with variability within the process specifications. The target Etch Rate for these lines is 620, with lower and upper specification of 545 and 695 respectively (i.e., 620 +/- 75). Etching is done in sets of 20 wafers. A sampling plan has been established which will randomly sample 5 wafers from each run for 40 subsequent runs, resulting in 200 wafers sampled from each line. Etch Rate will be measured at 4 separate locations on each wafer.
This results in 5 x 40 x 4 = 800 Etch Rate values per etching line. Based upon this sampling strategy, three sources of variation can be examined for each line: 1) within wafer; 2) between wafer within run; 3) between runs.
Importantly, equipment recalibration was performed after the 20th run. This allows run variation to be separated into two other sources: 3a) between runs within calibration stage; 3b) between calibration stages.
In this case study, we will demonstrate a variety of analyses on one of the etching lines. The exercises will ask you to conduct similar analyses on the other six etching lines.
The primary objectives of the analyses are:
The process begins with a silicon wafer. Wafers are sliced from a salami-shaped bar of 99.99% pure silicon (known as an 'ingot') and polished to extreme smoothness. Thin films of conducting, isolating or semiconducting materials – depending on the type of structure being made – are deposited on the wafer to enable the first layer to be printed on it. This important step is commonly known as 'deposition'.
As microchip structures 'shrink', the process of patterning the wafer becomes more complex. Advances in deposition, as well as etch and lithography – more on that later – are enablers of shrink and the pursuit of Moore's Law. These advances include the use of new materials and innovations that enable increased precision when depositing these materials.
The wafer is then covered with a light-sensitive coating called 'photoresist', or 'resist' for short. There are two types of resist: positive and negative.
The main difference between positive and negative resist is the chemical structure of the material and the way that the resist reacts with light. With positive resist, the areas exposed to ultraviolet light change their structure and are made more soluble – ready for etching and deposition. The opposite is true for negative resist, where areas hit by light polymerize, meaning they become stronger and more difficult to dissolve. Positive resist is most commonly used in semiconductor manufacturing because its higher resolution capability makes it the better choice for the lithography stage.
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Several companies around the world produce resist for semiconductor manufacturing, such as Fujifilm Electronics Materials, The Dow Chemical Company and JSR Corporation.
Lithography is a crucial step in the chipmaking process, because it determines just how small the transistors on a chip can be. During this stage, the chip wafer is inserted into a lithography machine (that's us!) where it's exposed to deep ultraviolet (DUV) or extreme ultraviolet (EUV) light. This light has a wavelength anywhere from 365 nm for less complex chip designs to 13.5 nm, which is used to produce some of the finest details of a chip – some of which are thousands of times smaller than a grain of sand.
Light is projected onto the wafer through the 'reticle', which holds the blueprint of the pattern to be printed. The system's optics (lenses in a DUV system and mirrors in an EUV system) shrink and focus the pattern onto the resist layer. As explained earlier, when light hits the resist, it causes a chemical change that enables the pattern from the reticle to be replicated onto the resist layer.
Getting the pattern exactly right every time is a tricky task. Particle interference, refraction and other physical or chemical defects can occur during this process. That's why, sometimes, the pattern needs to be optimized by intentionally deforming the blueprint, so you're left with the exact pattern that you need. Our systems do this by combining algorithmic models with data from our systems and test wafers in a process referred to as 'computational lithography'. The resulting blueprint might look different from the pattern it eventually prints, but that's exactly the point. Everything we do is focused on getting the printed patterns just right.
The next step is to remove the degraded resist to reveal the intended pattern. During 'etch', the wafer is baked and developed, and some of the resist is washed away to reveal a 3D pattern of open channels. Etch processes must precisely and consistently form increasingly conductive features without impacting the overall integrity and stability of the chip structure. Advanced etch technology is enabling chipmakers to use double, quadruple and spacer-based patterning to create the tiny features of the most modern chip designs.
As with resist, there are two types of etch: 'wet' and 'dry'. Dry etching uses gases to define the exposed pattern on the wafer. Wet etching uses chemical baths to wash the wafer. Companies such as Lam Research, Oxford Instruments and SEMES develop semiconductor etching systems.
Chips are made up of dozens of layers. So, it's important that etching is carefully controlled so as not to damage the underlying layers of a multilayer microchip structure or – if the etching is intended to create a cavity in the structure – to ensure the depth of the cavity is exactly right. When you consider that some microchip designs such as 3D NAND are reaching up to 175 layers, this step is becoming increasingly important – and difficult.
Once patterns are etched in the wafer, the wafer may be bombarded with positive or negative ions to tune the electrical conducting properties of part of the pattern. Raw silicon – the material the wafer is made of – is not a perfect insulator or a perfect conductor. Silicon’s electrical properties are somewhere in between. Directing electrically charged ions into the silicon crystal allows the flow of electricity to be controlled and transistors – the electronic switches that are the basic building blocks of microchips – to be created. This process is known as ‘ion implantation’.
After the ions are implanted in the layer, the remaining sections of resist that were protecting areas that should not be modified are removed.
The entire process of creating a silicon wafer with working chips consists of thousands of steps and can take more than three months from design to production. To get the chips out of the wafer, it is sliced and diced with a diamond saw into individual chips. Cut from a 300-mm wafer, the size most often used in semiconductor manufacturing, these so-called 'dies' differ in size for various chips. Some wafers can contain thousands of chips, while others contain just a few dozen.
The chip die is then placed onto a 'substrate'. This is a type of baseboard for the microchip die that uses metal foils to direct the input and output signals of a chip to other parts of a system. And to close the lid, a 'heat spreader' is placed on top. This heat spreader is a small, flat metal protective container holding a cooling solution that ensures the microchip stays cool during operation.